A Low Power and High Performance Ebcot Architecture of Jpeg2000 Encoding

We propose an architecture for Tier-1 of Embedded Block Coding With Optimized Truncation (EBCOT) in the JPEG2000 standard. The architecture is composed of a 16-bit parallel context generator and a 3-stage pipelined binary arithmetic encoder. The former is designed for low power consumption. The later is used to achieve an high throughput. The design is verified on an AMBA-based system as an accelerator. Compared with the best-known column-based method, we reduce the cycle count by 17%. Let the number of context-decision (CX, D) pairs be the lower bound on the cycle count, we have achieved 6% within the optimal.